A 12-Bit 96Msample/s double-data-rate (DDR) pipeline ADC with speed and noise optimization for CMOS image sensors
ISEEE), 2014 International Conference （2014）
摘要
In this paper, a 12-bit pipeline ADC with double-data-rate topology is proposed for high-speed CMOS image sensors (CIS). With a unique ping-pang architecture and a pseudo-noise cancellation scheme implemented, the designed ADC achieved a high sampling rate of 96Ms/s and with a good linearity and noise performance. The proposed ADC and image sensor chips are fabricated in the GSMC 0.13μm high-voltage mixed signal CMOS process. According to the simulation result, the SFDR performance is 77dB at 11.4375MHz input and DNL and INL are measured at -0.35LSB/+0.15LSB and -6LSB/+6LSB respectively. The area of the ADC is 1.85mm2. Powered with 3.3V power supply, the input range is ±1.8V and the power consumption of the ADC is 70mW.
更多查看译文
关键词
cmos image sensors,analogue-digital conversion,circuit optimisation,cis,ddr,gsmc high-voltage mixed signal cmos process,double-data-rate pipeline adc,double-data-rate topology,frequency 11.4375 mhz,high-speed cmos image sensors,noise optimization,ping-pang architecture,power 70 mw,pseudonoise cancellation scheme,size 0.13 mum,speed optimization,voltage 3.3 v,word length 12 bit,cmos image sensor (cis),double data rate (ddr),pipeline adc,accuracy,pipelines,noise,calibration,optimization
AI 理解论文
溯源树
样例
生成溯源树，研究论文发展脉络
Chat Paper
正在生成论文摘要